JPH0429104B2 - - Google Patents

Info

Publication number
JPH0429104B2
JPH0429104B2 JP10796282A JP10796282A JPH0429104B2 JP H0429104 B2 JPH0429104 B2 JP H0429104B2 JP 10796282 A JP10796282 A JP 10796282A JP 10796282 A JP10796282 A JP 10796282A JP H0429104 B2 JPH0429104 B2 JP H0429104B2
Authority
JP
Japan
Prior art keywords
channel device
access request
circuit
clock
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP10796282A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58223833A (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10796282A priority Critical patent/JPS58223833A/ja
Publication of JPS58223833A publication Critical patent/JPS58223833A/ja
Publication of JPH0429104B2 publication Critical patent/JPH0429104B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/30—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal with priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
JP10796282A 1982-06-23 1982-06-23 ダイレクト・メモリ・アクセス制御方式 Granted JPS58223833A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10796282A JPS58223833A (ja) 1982-06-23 1982-06-23 ダイレクト・メモリ・アクセス制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10796282A JPS58223833A (ja) 1982-06-23 1982-06-23 ダイレクト・メモリ・アクセス制御方式

Publications (2)

Publication Number Publication Date
JPS58223833A JPS58223833A (ja) 1983-12-26
JPH0429104B2 true JPH0429104B2 (en]) 1992-05-18

Family

ID=14472474

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10796282A Granted JPS58223833A (ja) 1982-06-23 1982-06-23 ダイレクト・メモリ・アクセス制御方式

Country Status (1)

Country Link
JP (1) JPS58223833A (en])

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6250946A (ja) * 1985-08-30 1987-03-05 Hitachi Ltd Ｄｍａ制御方式
US4901234A (en) * 1987-03-27 1990-02-13 International Business Machines Corporation Computer system having programmable DMA control
JPS6454562A (en) * 1987-08-26 1989-03-02 Fujitsu Ltd Data transfer control system
US5142672A (en) * 1987-12-15 1992-08-25 Advanced Micro Devices, Inc. Data transfer controller incorporating direct memory access channels and address mapped input/output windows
US6701397B1 (en) 2000-03-21 2004-03-02 International Business Machines Corporation Pre-arbitration request limiter for an integrated multi-master bus system

Also Published As

Publication number Publication date
JPS58223833A (ja) 1983-12-26

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